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Biosketch
Subrahmanyam Mula received the B.E. degree in electronics and communication engineering from Andhra University, Visakhapatnam in 2001, and the M.Tech. degree in microelectronics and VLSI design from IIT Kharagpur in 2003, and Ph.D. degree from Department of Electronics and Electrical Communication Engineering, IIT Kharagpur in 2018. From 2003 to 2014, he was with Intel, Bengaluru where he was involved in front-end design verification of gigabit Ethernet switches, processors, chip-sets, and GPUs. He supported six generations of Intel GPUs from Eaglelake (Gen4) on 65nm to Skylake (Gen9) on 14nm at various levels such as architecture, RTL, Verification, GLS, STA, DFT and Post Si Debug. His current research interests include VLSI architectures for real time signal processing applications and adaptive learning systems.
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Research
My research interests span the broad area of VLSI architectures for statistical signal processing algorithms. My current research mainly focuses on developing efficient VLSI architectures for real-time adaptive filtering applications. For achieving the best performance-flexibility trade-off of the complex adaptive filtering algorithms, I focus on co-design of algorithm and architecture in an intertwined way rather than designing them in isolation.
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Teaching
· Digital Systems (UG) (July - Dec 2019, 2020, 2021, 2023 and 2024)
· Digital Circuits Lab (UG) (July - Dec 2019, 2022, 2023 and 2024)
· VLSI Architectures for signal processing and machine learning (Theory & Lab) (UG & PG) (Jan - May 2020, 2021, 2022, 2023, 2024)
. VLSI Design (Theory & Lab) (PG) (July - Dec 2020, 2021, 2022, 2023, 2024)
. Principles of SoC Functional Verification (PG) ( Jan - May 2023)
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Research Group
PhD Students:
Ongoing:
1. Ganjimala Pavankumar (PMRF Fellow, July 2020 - ) , Research Area : Algorithms and architectures for nonlinear adaptive filtering applications
2. Rooha Ramzid Ahamed (July 2022 - ), Research area : VLSI architectures for real-time signal processing/machine learning applications
3. Jayarani M A (UGC NET Fellowship July 2022 - ) (Jointly with Dr. Sabarimalai Manikandan) , Research area : Low power VLSI architectures for biomedical signal processing
4. Raghavendra K, (Visvesvaraya Fellow, July 2024 - ) (Jointly with Dr. Swaroop Shaoo), Research area : Algortithms and VLSI Architectures for Radar Signal Processing
5. Ashish Biju Varghese, (Visvesvaraya Fellow, July 2024 - ) (Jointly with Dr. Sabarimalai Manikandan) , Research area : Algortithms and VLSI Architectures for Radar Signal Processing
6. Vijay Gopal (External Registration, NPOL Kochi, July 2024 - ) , Research area: Low power VLSI Architectures for Signal Processing Applications
MS Students:
Ongoing:
1. Vishnu P S (July 2022 - ) , Research area: VLSI signal processing
Completed:
1. Daney Alex (Jan 2020 - September 2022) , Thesis title: VLSI Architectures for Adaptive Filters under non-Gaussian Signal and Noise Conditions
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Additional Information
TitleSponsored ProjectsDescription
Project Title Funding Agency Duration Role HARKAL: Hardware Accelerated Robust Kernel Adaptive Learning Start-up Research Grant (SERB) Jan 2021 - Jan 2023 PI Energy Efficient Distributed Estimation and Control of Networked Robots and its Implementation Architectures IIT Palakkad Technology IHub Foundation (IPTIF) June 2021 - June 2026 Co-PI Development of Real-time Compact AI-Enabled UWB Radar Based See-Through-wall Human Sensing System
Ministry of Electronics and Information Technology (MeitY)June 2023 - Jan 2027 PI TitlePublicationsDescriptionJournals:
1. V. C. Gogineni, R. Sambangi, D. Alex, S. Mula and S. Werner, “Algorithm and Architecture Design of Random Fourier Features-Based Kernel Adaptive Filters,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 2, pp. 833-845, Feb. 2023.
2. D. Alex, V. C. Gogineni, S. Mula and S. Werner, "Novel VLSI Architecture for Fractional-order Correntropy Adaptive Filtering Algorithm", in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 30, no. 7, pp. 893-904, July 2022.
3. S. R. K. Vadali, S. Mula, P. Ray and S. Chakrabarti, "Area Efficient VLSI Architectures for Weak Signal Detection in Additive Generalized Cauchy Noise," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 6, pp. 1962-1975, June 2020.
4. S. Mula, V. C. Gogineni, A. S. Dhar, “Robust Proportionate Adaptive Filter Architectures under Impulsive Noise,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no.5, pp. 1223-1227, May 2019.
5. S. Mula, V. C. Gogineni, A. S. Dhar, “Algorithm and VLSI Architecture Design of Proportionate-type LMS Adaptive Filters for Sparse System Identification,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no.9, pp. 1750-1762, Sept. 2018.
6. V. C. Gogineni and S. Mula, “Proportionate-type Adaptive Filtering under Maximum Correntropy Criterion for Identifying Systems with Variable Sparsity,” Digital Signal Processing (ELSEVIER), vol. 79, pp. 190-198, Aug. 2018.
7. V. C. Gogineni and S. Mula, “Logarithmic Cost based Constrained Adaptive Filtering Algorithms for Sensor Array Beamforming,” IEEE Sensors Journal, vol. 18, no. 14, pp. 5897-5905, July 2018.
8. S. Mula, V. C. Gogineni, A. S. Dhar, “Algorithm and Architecture Design of Adaptive Filters With Error Nonlinearities,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 9, pp. 2588-2601, Sept. 2017.
9. B. K. N. Srinivasarao, V. C. Gogineni, S. Mula, and I. Chakrabarti, “A Novel Framework for Compressed Sensing based Scalable Video Coding”, Signal Processing: Image Communication (ELSEVIER), vol. 57, pp. 183-196, Sept. 2017.
10. S. R. K. Vadali, P. Ray, S. Mula, and P. K. Varshney, “Linear Detection of a Weak Signal in Additive Cauchy Noise,” IEEE Transactions on Communications, vol. 65, no. 3, pp. 1061-1076, March 2017.
Conferences:
1. Vishnu P S, S. Mula “A Parameterized VLSI Architecture for Real-Time Inversion of Square Matrices and Moore-Penrose Pseudoinversion of Rectangular Matrices” 2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Nancy, France, 2024 (Accepted).
2. S. Mula “Wavelet Domain Proportionate Adaptive Filtering Algorithms for Impulsive Noise Environments under correlated input conditions” 2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Nancy, France, 2024 (Accepted).
3. G. Pavankumar, S. Mula “A proportionate type block-oriented functional link adaptive filter for sparse nonlinear systems ” 2024 International Symposium on Circuits and Systems (ISCAS), Singapore, Singapore, 2024, pp. 1-5.
4. Jayarani M A, M Sabarimalai Manikandan, S. Mula “Effective Sparse Reconstruction Algorithms for Compressed ECG Sensing with Deterministic Binary Block Diagonal Sensing Matrix” 2024 16th International Conference on Electronics, Computers and Artificial Intelligence (ECAI), Iasi, Romania, 2024, pp. 1-6.
5. G. Pavankumar, S. Mula “A Low Complexity Block-oriented Functional Link Adaptive Filtering Algorithm” 2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Istanbul, Turkiye, 2023, pp. 1-5.
6. Jayarani M A, M Sabarimalai Manikandan, S. Mula “Performance Evaluation of Sparse Recovery Algorithms for Efficient Signal Reconstruction in Compressed PPG Sensing Node” 2023 IEEE 9th International Conference on Smart Instrumentation, Measurement and Applications (ICSIMA), Kuala Lumpur, Malaysia, 2023, pp.36-41.
7. P. K. Ganjimala, S. Mula, “High performance VLSI architecture for the modified SORT-N algorithms,“ 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Austin, TX, USA, pp. 2112-2116.
8. V. C. Gogineni, S. Mula, R. L. Das and M. Chakraborty, “Performance analysis of proportionate-type LMS algorithms,“ 2016 Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA), Poznan, Poland, 2016, pp. 177-181.
TitleInvited Talks and WorkshopsDescription• Five Day Hands-on Workshop on ”VLSI Design” under the C2S Project funded by the Ministry of Electronics and Information Technology (MeitY), Government of India, 24th to 28th June 2024 at Indian Institute of Technology Palakkad, Kerala
• “Chips for making better chips: VLSI design in the era of AI/ML” planery talk in ICSST Conference held at Model engineering college, Kochi, Kerala on 13th April 2024
• “VLSI architectures for signal processing” as part of hands on training on ”FPGA Architectures and Programming using Verilog“ held from 17th March to 22nd March 2024 at NIT Tiruchirappalli
• “VLSI Design and Recent trends” one day hands on workshop at IIT Palakkad held on 15th March 2024 as part of C2S project sponsored by MeitY.
• “Insights into VLSI Design” one day workshop on 1st March 2024 at Sri Eswer college of engineering, Coimbatore, Tamilnadu, India.
• “Algorithms to VLSI architectures” as part of 100 day RTL challenge on 26th Feb 2024 at Sahridaya College of Engineering and Technology, Kerala, India.
• “Custom IP design by mapping algorithms to architectures for real time signal processing applications” as part of FDP on ”Unleashing the Potential of System on-Chip and its Architecture’“ held from 15th to 20th January 2024 at St. Joseph’s College of Engineering and Technology, Palai, Kerala, India.
• “Mapping Algorithms to VLSI Architectures” as part of hands on training on ”FPGA Architectures and Programming using Verilog“ held from 5th June 2023 to 11th June 2023 at NIT Tiruchirappalli
• “CAD for Digital VLSI Design,“ as part of the five day online workshop on “The Art of IC design using EDA tools“ held from 15th-19th March, 2021 at Cochin University of Science and Technology, Kochi
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Publications
G. Pavankumar, S. MulaInternational Symposium on Circuits and Systems (ISCAS), Singapore, Singapore, 2024 (2024)Pavan Kumar Ganjimala; Subrahmanyam MulaIEEE International Symposium on Circuits and Systems (ISCAS), 2022 2112-2116 (2022)Daney Alex; Vinay Chakravarthi Gogineni; Subrahmanyam Mula; Stefan WernerIEEE Transactions on Very Large Scale Integration (VLSI) Systems (2022)Siva Ram Krishna Vadali; Subrahmanyam Mula; Priyadip Ray; Saswat ChakrabartiIEEE Transactions on Circuits and Systems I: Regular Papers 67 (6) 1962 - 1975 (2020)Subrahmanyam Mula ; Vinay Chakravarthi Gogineni ; Anindya Sundar DharIEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (5) 1223 - 1227 (2019)
