Patents

1. Neha Bajpai and Yogesh Singh Chauhan, "System for Temperature-Compensated Biasing Circuit Integrated With Amplifier by Utilizing GaAs-based HEMTs”, Indian Patent No.: 540950, app. No.: 202311003068, Granted: 06/06/2024.

2. Neha Bajpai and Yogesh Singh Chauhan, "A Power Amplifier Design to Compensate Frequency Dependent Behavior”, Indian Patent No.: 437210, app. No.: 202111060670, Granted: 04/07/2023.

Journals

5. A. Verma, N. Bajpai, D. Singh and N. Dhawan, "Modification of Dielectric Mixing Model for Optimized Microwave Absorbing Composites Tuned by Electromagnetic, Structural, and Geometrical Parameters," in IEEE Transactions on Components, Packaging and Manufacturing Technology, doi: 10.1109/TCPMT.2025.3637155.
 

4. MH. Ansari, S. Thakur, N. Bajpai, P. Maity, A. Lahgere, SA Ahsan, M. Shah, YS Chauhan, "Comprehensive analysis and investigation of GaN LNA for 3–4 GHz using different gate-drain spacing”, in Microelectronic Engineering, vol. 299, pp. 112361, May 2025, DOI: S0167931725000504.

3. N. Bajpai, P. Maity, M. Shah, A. Das and Y. S. Chauhan, "An Ultra-Low Noise Figure and Multi-Band Re-Configurable Low Noise Amplifier”, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 3, pp. 1006-1016, March 2023, DOI: 10.1109/TCSI.2022.3229135.

2. N. Bajpai and Y. S. Chauhan, "A multi-variable double impedance matching network design algorithm with design example of a low noise amplifier”, in Int J RF Microwave Comput-Aided Eng. vol. 32, pp. e23462, 2022, DOI: 10.1002/mmce.23462.

1. N. Bajpai, A. Pampori, P. Maity, M. Shah, A. Das and Y. S. Chauhan, "A Low Noise Power Amplifier MMIC to Mitigate Co-Site Interference in 5G Front End Modules”, in IEEE Access, vol. 9, pp. 124900-124909, 2021, 10.1109/ACCESS.2021.3108596.

Conferences

4. N. Bajpai and Y. S. Chauhan, ”A GaN Low Noise Amplifier Design Using Numerical Optimization,” 2024 8th IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Bangalore, India, 2024, pp. 1-3, 10.1109/EDTM58488.2024.10511494.

3. N. Bajpai and Y. S. Chauhan, ”Comparative Performance Analysis of Impedance Line Segmentation Algorithm”, IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Bengaluru, India, Mar. 2024 Poster.

2. N. Bajpai and Y. S. Chauhan, ”A GaN Only Reverse Recovery Time Limiter Circuit Integrated with A Low Noise Amplifier,” 26th International Symposium on VLSI Design and Test (VDAT-2022), Jammu, July 2022, 10.1080/02670836.2021.1946949.

1. N. Bajpai and Y. S. Chauhan, ”A Broadband Power Amplifier MMIC to Compensate the Frequency Dependent Behaviour,” 2021 IEEE MTT-S International Microwave and RF Conference (IMARC), 2021, pp. 1-4, 10.1109/IMaRC49196.2021.9714648.

Design of Analog Electronic Circuits and Systems (EE6001)